Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available High Definition (HD) video formats, the computational complexity of De full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, ill this paper, we present Dynamically Variable Step Search (DVSS) ME algorithm for Processing high definition video formats and a dynamically reconfigurable hardware efficiently implementing DVSS algorithm. The architecture for efficiently implementing DVSS algorithm. The simulation results showed that DVSS algorithm performs very close to FS algorithm by searching much fewer search locations than FS algorithm and it outperforms successful past search ME algorithms by searching more search locations than these algorithms. The proposed hardware is implemented in VHDL and is capable, of processing high definition video formats in real time. Therefore, it can be used in consumer electronics products for video compression, frame rate up-conversion and de-interlacing(1)

A high performance reconfigurable motion estimation hardware architecture

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and high frame rates, the computational complexity of full search (FS) ME algorithm is prohibitively high, while the PSNR obtained by fast search ME algorithms is low. Therefore, in this paper, we propose a new ME algorithm and a high performance reconfigurable systolic ME hardware architecture for efficiently implementing this algorithm. The proposed ME algorithm performs up to three different granularity search iterations in different size search ranges based on the application requirements. Simulation results showed that the proposed ME algorithm performs very close to FS algorithm, even though it searches much fewer search locations than FS algorithm. It outperforms successful fast search ME algorithms by searching more search locations than these algorithms. The proposed reconfigurable ME hardware is implemented in VHDL and mapped to a low cost Xilinx XC3S1500-5 FPGA. It works at 130 MHz and is capable of processing high definition and high frame rate video formats in real time. Therefore, it can be used in flat panel displays for frame rate conversion and de-interlacing, and in video encoders